The present invention relates to a registered memory module and, more particularly, to a memory module having a delay locked loop (hereinafter, referred to as a DLL) circuit in a register.
A technology using stub bustopology for a DQ bus and a clock bus (hereinafter, referred to as a related art) has been proposed for purpose of response to a high frequency band. In the related art, an external clock signal WCLK transmitted from a chip set (or memory controller) is distributed into a plurality of memory devices arranged on a substrate of each memory module. Meanwhile, in the related art, a command/address (hereinafter, referred to as a C/A) signal transmitted from the chip set to the memory module via an external C/A bus is latched to a C/A register (hereinafter, referred to as a register) arranged on the substrate of each memory module. Thereafter, the latched C/A signal is distributed into a corresponding memory device via an internal C/A bus from the register to each memory device, as an internal C/A signal.
Currently, a large number of types of memory modules having four to eighteen memory devices, depending on whether or not an ECC function is provided or whether or not which capacity is realized, have come into a market. Operating frequencies of the memory devices mounted on the single memory module are varied. On the other hand, in the related art, a method using an individual register is used corresponding to the operating frequencies and to the number of mounted memory devices. Because a set-up time and a hold time in a flip-flop forming a latch circuit are held to be appropriate.
However, the efficiency of parts in the case of designing and producing the single register capable of corresponding to any operating frequency and to any the number of mounted memory devices are higher than that in the case of designing and producing individual registers corresponding to operating frequencies and the number of mounted memory devices. In other words, a request is the appearance of a register independent of the number of mounted memory devices, capable of corresponding to a requested used frequency band. The used frequency band has, for example, a clock frequency of 200 to 300 MHz.